1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to methods for processing a semiconductor topography having openings etched within a dielectric layer.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
In the fabrication of microelectronic devices, numerous conductive structures, such as gate electrodes, contacts, vias and interconnects, may be formed in or above a semiconductor substrate isolated from one another by dielectric layers. At various stages in the fabrication of microelectronic devices, it may be necessary to form openings in the dielectric layers to allow for contact to underlying regions or layers. Generally, an opening through a dielectric layer exposing a diffusion region of a semiconductor substrate or an opening through a dielectric layer between a gate electrode and a first metal layer is called a “contact opening” or a “contact hole.” An opening in other dielectric layers such as an opening through an interlevel dielectric layer is referred to as a “via opening.” For purposes of this disclosure, however, “contact opening” may be used to refer to a contact opening and/or a via opening interchangeably. As such, a contact opening, as used herein, may expose a diffusion region such as, a source or drain, or may expose metallization such as, a local interconnect layer or gate structure.
After a contact opening has been formed within a dielectric layer, the opening may be cleaned. The cleaning process may remove small amounts of debris and residual material formed on sidewalls and/or the bottom surface of the contact opening during the formation of the contact opening and/or the removal of an overlying photoresist mask used to pattern the opening. Such a cleaning process, however, is not typically sufficient to remove metal oxide layers formed upon exposed conductive structures. In some cases, the deposition of a dielectric layer over metallization may oxidize an upper portion of the metallization, forming a metal oxide layer. Such a metal oxide layer may undesirably increase the contact resistance of the metallization. In particular, the resulting surface of the metallization may have a contact resistance of approximately 2000 ohms. Consequently, it may be advantageous to remove or prevent the formation of metal oxide layers within contact openings. Although etch chemistries for removing metal oxide materials exist, conventional metal oxide layer removal chemistries are typically apt to etch silicon materials as well. As such, in embodiments in which a plurality of contact openings are formed across a semiconductor topography with exposed silicon and metallization surfaces, an etch chemistry used to remove metal oxide may undesirably etch the exposed portions of silicon as well. Such an affinity to silicon may cause gouges within a semiconductor substrate or field-oxide regions of the semiconductor topography. In some cases, the gouges may undesirably affect the functionality of the device formed therefrom.
Accordingly, it would be advantageous to develop a method for removing metal oxide materials within contact openings. In particular, it would be beneficial to develop a method with a substantially higher etch selectivity to metal oxide than silicon materials. Such a method may advantageously offer a semiconductor topography with conductive structures having reduced contact resistances and silicon surfaces which have not been gouged.